Shifting register, gate driving apparatus and display apparatus

摘要

A shifting register, a gate driving apparatus and a display apparatus comprising the shifting register. The shifting register comprises a latch (21), a transmission gate (22), a first TFT (T1), a second TFT (T2), a third TFT (T3) and a first inverter (23), the first TFT (T1), having a gate connected to a reset (Reset) of the shifting register, a drain connected to a drain of the second TFT (T2) and an input (M) of the latch (21) respectively; the second TFT (T2), having a gate connected to an input (Input) of the shifting register, the third TFT (T3), having a gate connected to the inverting output of the latch (21), a drain connected to an input of the first inverter (23); an output of the transmission gate being connected to a drain of the third TFT (T3), an input of the transmission gate being connected to a clock signal input (CLOCK); the drain of the third TFT (T3) being connected to a non-inverting output (Output_Q) of the shifting register, an output of the first inverter being connected to an inverting output (Output_QB) of the shifting register. The shifting register achieves a signal shift with only one latch (21).

主权项

1. A shifting register, comprising: a latch, a transmission gate, a first TFT, a second TFT, a third TFT and a first inverter, wherein,
the first TFT, having a gate connected to a reset of the shifting register, a source connected to a high-level output of a driving power, and a drain connected to a drain of the second TFT and an input of the latch respectively; the second TFT, having a gate connected to an input of the shifting register, a source connected to a low-level output of the driving power; a non-inverting output of the latch being connected to a non-inverting control of the transmission gate, an inverting output of the latch being connected to an inverting control of the transmission gate; the third TFT, having a gate connected to the inverting output of the latch, a source connected to the low-level output of the driving power, and a drain connected to an input of the first inverter; an output of the transmission gate being connected to a drain of the third TFT, an input of the transmission gate being connected to a clock signal input; the drain of the third TFT being connected to a non-inverting output of the shifting register, an output of the first inverter being connected to an inverting output of the shifting register; if the first TFT is a p-type TFT, the second TFT and the third TFT are n-type TFTs; if the first TFT is a n-type TFT, the second TFT and the third TFT are p-type TFTs.