| 发明名称 |
Obstruction-Aware Cache Management |
| 摘要 |
Processors and methods disclosed herein include a cache memory unit, n processor cores where n≧1, a controller connected to the cache memory unit and to each of the n processor cores, and n obstruction monitoring units, where each obstruction monitoring unit is connected to the controller and to a different one of the n processor cores, and where during operation of the electronic processor, each obstruction monitoring unit is configured to detect an obstruction corresponding to an operation from the processor core connected to the obstruction monitoring unit before the operation executes in the cache memory unit. |
| 申请公布号 |
US2015100740(A1) |
申请公布日期 |
2015.04.09 |
| 申请号 |
US201314046614 |
申请日期 |
2013.10.04 |
| 申请人 |
The Penn State Research Foundation |
发明人 |
Wang Jue;Xie Yuan |
| 分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An electronic processor, comprising:
a cache memory unit; n processor cores, wherein n≧1; a controller connected to the cache memory unit and to each of the n processor cores; and n obstruction monitoring units, wherein each obstruction monitoring unit is connected to the controller and to a different one of the n processor cores, wherein during operation of the electronic processor, each obstruction monitoring unit is configured to detect an obstruction corresponding to an operation from the processor core connected to the obstruction monitoring unit before the operation executes in the cache memory unit. |
| 地址 |
University Park PA US |
