SEMICONDUCTOR DEVICE INCLUDING A CLOCK ADJUSTMENT CIRCUIT

摘要

Disclosed herein is a semiconductor device that includes a first circuit comprising a plurality of first logic elements coupled in cascade and configured, in response to first and second clock signals and a control signal, to produce control information that indicates a first number of the first logic elements through which the control signal has been propagated during a period defined by a first change in logic level of the first clock signal and by a second change in logic level of the second clock signal, the first and second changes occurring adjacently to each other in same directions as each other, and a second circuit comprising a delay circuit configured to receive the first clock signal and the control information and to produce a third clock signal by delaying the first clock signal by an amount responsive to the control information.

主权项

1. A semiconductor device comprising:
a phase difference detection circuit configured, responsive to first and second clock signals each clocking between first and second logic levels, to generate a first control signal that takes an active level, the active level being defined by a first change of the first clock signal from the first logic level to the second logic level and by a second change of the second clock signal from the first logic level to the second logic level, the first and second changes occurring adjacently to each other; a register circuit including a plurality of first logic elements coupled in series and receiving the first control signal and a second control signal, the register circuit being configured to pass the second control signal through first logic elements of the plurality of first logic elements during the active level of the first control signal to generate control information that indicates a first number of the plurality of first logic elements through which the second control signal has passed during the active level of the first control signal; and a delay circuit receiving the first clock signal and the control information, the delay circuit being configured to produce a third clock signal by delaying the first clock signal by an amount responsive to the control information.