COMPLEX LAYOUT-BASED TOPOLOGICAL DATA ANALYSIS OF ANALOG NETLISTS TO EXTRACT HIERARCHY AND FUNCTIONALITY

摘要

A system and method for reverse synthesizing an integrated circuit from a netlist. A netlist extracted from a device under review is received and converted to a connected graph. Blocks of cells are identified within the connected graph and a circuit model is formed from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells.

主权项

1. A method, comprising:
receiving a netlist; converting the netlist to a connected graph; identifying blocks of cells within the connected graph; and forming a circuit model from the blocks of cells, wherein forming includes iteratively building more complex blocks of cells from simpler blocks of cells.