| 发明名称 |
FERROELECTRIC MEMORY DEVICE |
| 摘要 |
A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number. |
| 申请公布号 |
US2015098263(A1) |
申请公布日期 |
2015.04.09 |
| 申请号 |
US201414485494 |
申请日期 |
2014.09.12 |
| 申请人 |
FUJITSU SEMICONDUCTOR LIMITED |
发明人 |
HIRAYAMA Tomohisa;Morita Keizo;Shinozaki Naoharu |
| 分类号 |
G11C11/22 |
主分类号 |
G11C11/22 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A ferroelectric memory device, comprising:
a memory array including a plurality of ferroelectric memory cells; a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data; and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number. |
| 地址 |
Yokohama-shi JP |
