发明名称 |
High-Speed Receiver Architecture |
摘要 |
A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm. |
申请公布号 |
US2015098710(A1) |
申请公布日期 |
2015.04.09 |
申请号 |
US201414480085 |
申请日期 |
2014.09.08 |
申请人 |
ClariPhy Communications. Inc. |
发明人 |
Agazzi Oscar Ernesto;Crivelli Diego Ernesto;Carrer Hugo Santiago;Hueda Mario Rafael;Luna German Cesar Augusto;Grace Carl |
分类号 |
H04B10/40 |
主分类号 |
H04B10/40 |
代理机构 |
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代理人 |
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主权项 |
1. A transceiver chip for communication at a data rate of 10 Gbps or higher over a fiber optic, the transceiver chip comprising:
a host interface for receiving digital data in electrical form at a data rate of 10 Gbps or higher, the received digital data in a host format; a laser driver port for generating an electrical signal modulated by the received data in electrical form, the electrical signal suitable for driving a laser driver; transmit path circuitry coupled between the host interface and the laser driver port; a TIA port for receiving an electrical signal from a transimpedance amplifier, the electrical signal modulated by data at a data rate of 10 Gbps or higher; and receive path circuitry coupled between the TIA port and the host interface, the host interface further for transmitting digital data in electrical form at a data rate of 10 Gbps or higher, the transmitted digital data also in the host format. |
地址 |
Irvine CA US |