| 摘要 |
<p>A clock generator circuit generates a wanted RF clock signal by using an up-converter, a spurious tone cancellation circuit, a controller, and at least two clock driver/dividers. The spurious tone cancellation circuit includes a tone detection circuit and a tone generation circuit. The up-converter mixes modulation signals with local quadrature RF clock signals to create an up-converted signal having a frequency tone equal to a desired frequency of the wanted RF clock signal. The first clock driver/divider amplifies and clips the up-converted signal into a first-clipped clock signal. The tone detection circuit detects the amplitude and phase of unwanted tones of the first-clipped clock signal in the baseband domain and provides information to the controller, which controls the tone generation circuit to cancel the unwanted tones and create a compensated version of first-clipped clock signal. The second clock driver/divider further amplifies and clips the compensated version of first-clipped clock signal to generate the wanted RF clock signal.</p> |
