An embodiment of the invention provides a chip package including a semiconductor substrate (100) having a first surface (100a) and a second surface (100b) opposite thereto. A dielectric layer (130) is overlying the first surface of the semiconductor substrate and comprises an opening exposing a conducting pad (150). A side recess (200) is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface (100a) towards the second surface (100b). An upper recess is on at least a first side of the dielectric layer outside the conducting pad. A conducting layer is electrically connected to the conducting pad (150) and extends to the upper recess and the side recess.
