发明名称 半導体装置
摘要 <p>An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.</p>
申请公布号 JP5696009(B2) 申请公布日期 2015.04.08
申请号 JP20110195554 申请日期 2011.09.08
申请人 发明人
分类号 H01L21/8242;C23C14/08;G11C11/401;H01L27/10;H01L27/108;H01L29/786 主分类号 H01L21/8242
代理机构 代理人
主权项
地址