发明名称 非ソースシンクロナスインターフェイスのための入出力の強化
摘要 <p>An interface for use of device whose core circuitry operates in one voltage domain, but exchanges signal with another device (or“host”) according a different voltage domain, and the use of such an interface for supplying data using a double data rate (DDR) transfer, is presented. One concrete example of this situation is a memory card, where the internal circuitry uses one voltage range for its core operating voltages, but exchanges signals with a host using different, input/output voltage range. According to a general set of aspects, the interface receives data signals from the device at the device's core operating voltage domain, individually level shifts these to the input/output voltage domain, and then combines them into a DDR signal for transfer to the host device, where a (non-level shifted) clock signal from the host device is used as the select signal to form the DDR data signal.</p>
申请公布号 JP5695732(B2) 申请公布日期 2015.04.08
申请号 JP20130501356 申请日期 2011.03.21
申请人 发明人
分类号 G06F13/16;G11C11/4076;G11C11/409 主分类号 G06F13/16
代理机构 代理人
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