Layer formation with reduced channel loss

摘要

Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

主权项

1. A device comprising:
a semiconductor device region; a gate region coupled to an upper surface of said semiconductor device region and extending upwardly from the upper surface to define a plurality of gate sidewalls; a source region coupled to the upper surface of said semiconductor device region laterally adjacent said gate region, said source region having a proximal end adjacent said gate region and an enlarged height distal end; a drain region coupled to the upper surface of said semiconductor device region laterally adjacent said gate region, said drain region having a proximal end adjacent said gate region and an enlarged height distal end; a first insulating layer above the semiconductor device region and coupled to the sidewalls of said gate region and an upper surface of the proximal end of said source and drain regions; and a second insulating layer coupled to the distal end of said source and drain regions, an upper surface of said gate region, said first insulating layer, and a lower surface of said semiconductor device region; wherein a portion of the semiconductor device region under said first and second insulating layers is doped.