Synthesis of clock gated circuit

摘要

Technology for synthesizing a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the circuit's behavior, or other functionality, via multiple statements, including a conditional statement. The technology includes analyzing statements upstream and/or downstream from the conditional statement, identifying one or more statements having dependency relationships with the conditional statement and inferring one or more potential clock domains for logic associated with the identified statements.

主权项

1. A non-transitory computer-readable storage medium having instructions stored therein for causing a processor to perform a process of synthesizing a behavioral description of a circuit into a structural description of the circuit, the process comprising:
receiving the behavioral description of the circuit, the behavioral description including a first statement that is associated with a condition; identifying the condition associated with the first statement; identifying one or more other statements associated with the first statement, including:
determining a downstream statement that depends on the first statement, and/ordetermining an upstream statement upon which the first statement depends; inferring one or more potential clock domains gated by the condition for logic associated with the first statement and the one or more other statements; scheduling the logic associated with the first statement and the one or more other statements according to the one or more potential clock domains; and generating the structural description of the circuit, the structural description including a structural description of the scheduled logic.