Compressor inputs from scan register output and input through flip-flop

摘要

The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

主权项

1. A device comprising:
A. scan data input leads; B. a scan clock lead; C. a scan enable lead; D. scan registers, each scan register having a data input coupled to one of the scan data input leads, a clock input coupled to the scan clock lead, a control input coupled to the scan enable lead, and a scan output; E. an inverter having an input connected to the scan clock lead and an output; F. flip-flops, each flip-flops having a data input coupled to one of the scan data input leads, a clock input coupled to the output of the inverter, and a data output; and G. a compressor circuit having pairs of data inputs, each pair of data inputs having a first data input coupled to the scan output of a certain scan register and a second data input coupled to the data output of a flip-flop that has a data input connected to the same scan data input lead as the certain scan register.