Semiconductor device

摘要

To provide a semiconductor device with high reliability in operation, in which data in a volatile memory can be saved to a non-volatile memory. For example, the semiconductor device includes an SRAM provided with first and second data storage portions and a non-volatile memory provided with third and fourth data storage portions. The first data storage portion is electrically connected to the fourth data storage portion through a transistor, and the second data storage portion is electrically connected to the third data storage portion through a transistor. The transistors are turned off when the SRAM operates, and the transistors are turned on when the SRAM does not operate, so that data in the SRAM is saved to the non-volatile memory. Precharge is performed when the SRAM is restored.

主权项

1. A semiconductor device comprising a plurality of memory elements arranged in a matrix, each memory element including:
a first memory circuit comprising a first inverter, a second inverter, a first data storage portion and a second data storage portion; and a second memory circuit comprising a third data storage portion, wherein the first data storage portion is electrically connected to a bit line through a first transistor; wherein the second data storage portion is electrically connected to an inverted bit line through a second transistor; wherein the first transistor and the second transistor are electrically connected to a first word line; wherein the third data storage portion is electrically connected to the second data storage portion through a third transistor; wherein the third transistor is electrically connected to a second word line; wherein the third data storage portion is electrically connected to one electrode of a capacitor; wherein the other electrode of the capacitor is electrically connected to a low potential power source line; wherein an input terminal of the first inverter and an output terminal of the second inverter are directly connected to the first transistor; wherein an output terminal of the first inverter and an input terminal of the second inverter are directly connected to the second transistor; wherein the second data storage portion is directly connected to the third transistor; wherein the second memory circuit is configured to save data in the second data storage portion to the third data storage portion immediately before supply of power to the first memory circuit is stopped; wherein the first data storage portion is not electrically connected to any circuit configured to save data in the first data storage portion before supply of power to the first memory circuit is stopped; wherein the first data storage portion and the second data storage portion are configured to be precharged in restoring the first memory circuit, thereby reading data from the third data storage portion to the second data storage portion; wherein each of the first transistor and the second transistor includes a silicon region; and wherein the third transistor includes an oxide semiconductor region.