2-D gather instruction and a 2-D cache

摘要

A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor. The two-dimensional (2-D) cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a two-dimensional structure of the 2-D image.

主权项

1. A processor comprising:
a pre-fetch unit to fetch one or more instructions, a decode unit to decode the one or more instructions, wherein the one or more instructions include a two-dimensional (2-D) gather instruction, an execution unit to perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor, and a two-dimensional (2-D) cache to store the one or more sub-blocks of data in multiple cache lines, to support access to more than one cache line in a single processing cycle, to preserve a two-dimensional structure of the 2-D image, and to support mapping of the one or more sub-blocks to avoid read conflict after loading the one or more sub-blocks, wherein the 2-D cache includes
a plurality of sets and a plurality of ways, andan access logic to map the one or more sub-blocks on to the plurality of sets and the plurality of ways and to perform a 2-D cache lookup, wherein the cache look-up includes
identifying a memory block within the 2-D cache using the set and the way of the 2-D cache,retrieving content of a tag field within the memory block, anddetermining if a data stored in the memory block is evicted.