Signal processing circuit, image scanner, and image forming apparatus

摘要

A signal processing circuit includes a generator, a transmission unit, a control unit, and a mode selector. The generator generates a process-required signal. The transmission unit transmits the process-required signal to a unit disposed after the transmission unit. The control unit supplies respective control signal to the generator and transmission unit. The control unit includes a reference clock generator constantly operated for generating a reference clock signal when the signal processing circuit is operated. The mode selector selects and shifts an operating mode of the signal processing circuit between a first mode and a second mode. In the first mode, the generator and transmission unit are supplied with respective normal control signal from the control unit for a normal operation. In the second mode, the generator is supplied with a control signal different from the normal control signal, and the transmission unit is supplied with the same normal control signal.

主权项

1. A signal processing circuit configured to operate in at least a first mode and a second mode consuming relatively less power than the first mode, the signal processing circuit comprising:
a timing controller including, a reference clock generator configured to generate a reference clock signal irrespective of whether the timing controller is operating in the first mode or the second mode, a plurality of first signal generators configured to generate, based on the reference clock, first control signals only if the signal processing circuit is operating in the first mode, a plurality of second signal generators configured to generate, based on the reference clock, second control signals if the signal processing circuit is operating in any one of the first mode and the second mode, and a mode selector to select and shift an operating mode of the signal processing circuit between the first mode and the second mode; and a data transmitter configured to transmit digital image data, a line synchronization signal and a differential clock signal to an image processing unit based on at least one of the second control signals such that the image processing unit receives and processes the line synchronization signal and a differential clock signal irrespective of whether the signal processing circuit is operating in the first mode or the second mode.