Method and equipment for testing semiconductor apparatuses simultaneously and continuously

摘要

A method for testing a plurality of semiconductor apparatuses, the method including mounting a plurality of semiconductor apparatuses on a first test board, wherein the plurality of semiconductor apparatuses include test circuits, loading test software into the test circuits, performing, by using the test circuits, self-tests on the plurality of semiconductor apparatuses based on the test software, and removing the plurality of semiconductor apparatuses, which have completed the self-tests, from the first test board. Upon completion of the loading of the test software, the test software is loaded into test circuits of a plurality of semiconductor apparatuses on a second test board, while the self-tests are performed on the plurality of semiconductor apparatuses on the first test board.

主权项

1. A method of testing a plurality of semiconductor apparatuses, the method comprising:
mounting a plurality of semiconductor apparatuses on a first test board, wherein the plurality of semiconductor apparatuses include test circuits; loading test software into the test circuits; performing, by using the test circuits, self-tests on the plurality of semiconductor apparatuses based on the test software; removing the plurality of semiconductor apparatuses, which have completed the self-tests, from the first test board; and continuously supplying power from a start of the self-tests on the plurality of semiconductor apparatuses on the first test board until completion of the self-tests on a plurality of semiconductor apparatuses on a last test board, wherein upon completion of the loading of the test software, the test software is loaded into test circuits of a plurality of semiconductor apparatuses on a second test board by disconnecting the first test board from a test signal line and connecting the second test board to the test signal line, while the self-tests are performed on the plurality of semiconductor apparatuses on the first test board, and a time of the self-tests on the plurality of semiconductor apparatuses on the first test board is overlapped with at least a portion of a time of self-tests on the plurality of semiconductor apparatuses on the second test board.