Lumped aggressor model for signal integrity timing analysis

摘要

A lumped aggressor model is used to simulate multiple aggressor nets acting on a victim net. By lumping the aggressor nets together into a single input port, a single voltage excitation may be applied to the input port to simulate the model during static timing analysis. However, a record of each individual aggressor net and several associated attributes for each aggressor net is maintained such that the individual lumped aggressor nets may still be modeled as separate contributions to the attack on the victim net.

主权项

1. A system for analyzing the timing of a circuit design, the system comprising:
a memory to store the design including instances of a plurality of nets; a processor configured to:
identify a victim net in the plurality of nets,identify a plurality of aggressor nets for the victim in the plurality of nets,for each aggressor net in the plurality of identified aggressor nets:
estimate a glitch created by the aggressor net,for an aggressor net having a glitch below a predetermined threshold, add the aggressor net to a lumped aggressor model such that each aggressor net in the lumped aggressor model is electrically connected to a shared node;for an aggressor net having a glitch above a predetermined threshold, model the aggressor net separately; andsimulate the victim net, with reference to the lumped aggressor model or the separately modeled aggressor nets, to estimate the timing for the victim net;wherein during simulation, for each aggressor net in the lumped aggressor model, the glitch for each aggressor is simulated individually using an associated driver waveform.