Systems and methods for latency and measurement uncertainty management in stimulus-response tests

摘要

Disclosed are systems and methods for managing testing unit latency and measurement uncertainty in computer-based stimulus-response tests. An estimated latency LE and an associated measurement uncertainty are determined as characteristics of a particular testing unit. LE is used as offset for all measurements taken on the testing unit, and results treated subject to the characteristic measurement uncertainty when determining test-taker performance. Estimated actual response times RTE are processed subject to a confidence value determined from the uncertainty. Uncertainty propagation determines test metrics involving a plurality of estimated actual response times RTE, where cumulative uncertainty is reported as a confidence rating in the metric. Overall test results (e.g., pass vs. fail) based on one or more metrics are also reported according to a confidence rating associated with the cumulative uncertainty propagated through the relevant metrics. Various calibration techniques are disclosed for determining the latency estimate LE and associated uncertainty values.

主权项

1. A processor-based method for scoring a stimulus-response test for a test taker with a confidence value based on response-time measurement uncertainty, the method comprising:
providing a testing unit, the testing unit comprising: a processor, an input device accessible to a test taker, an output device accessible to the test taker, an output data path connecting the processor to the output device, and an input data path connecting the input device to the processor; administering, with the testing unit, a stimulus-response test to the test-taker, administering the stimulus-response test comprising conducting a plurality of stimulus-response rounds, each of the plurality of stimulus-response rounds comprising:
sending a stimulus signal from the processor to the output device via the output data path, the stimulus signal sent from the processor at a first time t1, the stimulus signal causing the output device to output a stimulus and prompting the test taker to respond to the stimulus at the input device;receiving a response signal from the input device at the processor via the input data path, the response signal received at the processor at a second time t2;determining, with the processor, a round-trip signal time TRTS comprising a time interval between the first and second times;determining, with the processor, an estimated actual response time RTE to be a difference between the round trip signal time TRTS and a latency estimate LE, the latency estimate LE representing an estimate of a combination of: an output latency time between the first time t1 and a time that the stimulus is output from the output device; and an input latency time between a time that the test taker responds to the stimulus at the input device and the second time t2; determining, with the processor, one or more uncertainty values representing uncertainty associated with the plurality of estimated actual response times RTE; determining, with the processor, a performance indicator for the test taker, the performance indicator based on the plurality of estimated actual response times RTE; and determining, with the processor, a confidence value, the confidence value based on the one or more uncertainty values and representative of a confidence in the performance indicator.