| 主权项 |
1. A system for converting an analog signal into a digital signal, comprising:
an analog-to-digital converter (ADC) having an input terminal for receiving the analog signal, a clock input terminal for receiving an input clock signal, and an output terminal for outputting the digital signal; and a clock-halting circuit, connected to the clock input terminal of the ADC, for halting the input clock signal to the ADC based on an external trigger signal, wherein the trigger signal toggles between logic high and low states, and wherein the clock-halting circuit includes:
a synchronizer having an input terminal for receiving the trigger signal, a clock input terminal for receiving the input clock signal, and an output terminal for outputting a synchronous trigger signal;a counter circuit having an input terminal connected to the output terminal of the synchronizer for receiving the synchronous trigger signal and a clock input terminal for receiving the input clock signal, wherein the counter circuit starts a count of a predetermined set of count values after the trigger signal toggles between the logic high and low states, and wherein the predetermined set of count values corresponds to a predetermined time period; anda clock-halting latch, connected between the counter circuit and the clock input terminal of the ADC, for halting the input clock signal to the ADC for the predetermined time period. |
