| 发明名称 |
Reduction of single event upsets within a semiconductor integrated circuit |
| 摘要 |
A circuit includes a complimentary metal-oxide semiconductor (CMOS) storage element implemented within a p-type substrate and an n-well implemented within the p-type substrate that is independent of the storage element. The n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well. |
| 申请公布号 |
US9000529(B1) |
申请公布日期 |
2015.04.07 |
| 申请号 |
US201213666159 |
申请日期 |
2012.11.01 |
| 申请人 |
Xilinx, Inc. |
发明人 |
Jain Praful;Karp James;Hart Michael J.;Tanikella Ramakrishna K. |
| 分类号 |
H01L21/70;H01L29/06 |
主分类号 |
H01L21/70 |
| 代理机构 |
|
代理人 |
Cuenot Kevin T. |
| 主权项 |
1. A circuit, comprising:
a complimentary metal-oxide semiconductor (CMOS) storage element implemented within a p-type substrate; and an n-well implemented within the p-type substrate that is independent of the storage element; wherein the n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well; wherein the n-well is separated from the storage element by a region of the p-type substrate; and wherein the circuit further comprises at least one mitigating circuit element within the region. |
| 地址 |
San Jose CA US |
