Information processing apparatus, serial communication system, method of initialization of communication therefor, and serial communication apparatus

摘要

The disclosure provides a technique of enabling to confirm the state of a partner apparatus in high-speed serial communication. An information processing apparatus including a master and a slave which is connected with the master by a plurality of signal lines to be able to make serial communication therewith, the master comprises: a decision unit configured to decide a change in signal level of a data signal line, and a switching unit arranged between the data signal line and the decision unit, and configured to switch whether to invert a logical value based on the fact that the decision unit has decided a change in signal level of the data signal line.

主权项

1. A serial communication system including a master apparatus and a slave apparatus, wherein
said master apparatus and said slave apparatus are connected by: a first clock signal line configured to transmit a first clock signal from said master apparatus to said slave apparatus, a first data signal line configured to transmit a first data signal from said master apparatus to said slave apparatus, a second clock signal line configured to transmit a second clock signal from said slave apparatus to said master apparatus, and a second data signal line configured to transmit a second data signal from said slave apparatus to said master apparatus, said master apparatus comprises: a first decision unit configured to decide whether the second data signal line has been asserted, a first switching unit arranged between the second data signal line and said first decision unit, and configured to control whether to invert a logical value, a first driving unit configured to control to assert the first data signal line for a period of time longer than at least a cycle of the first clock signal, a first cancellation unit configured to control to invert, when said first decision unit detects that the second data signal line has been asserted for a period of time longer than at least a cycle of the second clock signal after said first driving unit asserted the first data signal line, a logical value by said first switching unit while cancelling the assertion of the first data signal line, and a first state decision unit configured to control to cancel, when said first decision unit detects that the second data signal line has not been asserted for a period of time longer than at least the cycle of the second signal after said first cancellation unit canceled the assertion of the first data signal line, the inversion of the logical value by said first switching unit while deciding that said slave apparatus is in a communicable state, and said slave apparatus comprises: a second decision unit configured to decide whether the first data signal line has been asserted, a second switching unit arranged between the first data signal line and said second decision unit, and configured to control whether to invert a logical value, a second driving unit configured to control to invert, when said second decision unit detects that the first data signal line has been asserted for a period of time longer than at least the cycle of the first clock signal, a logical value by said second switching unit while asserting the second data signal line for a period of time longer than at least the cycle of the second clock signal, and a second state decision unit configured to control to cancel, when said second decision unit detects that the first data signal line has not been asserted for a period of time longer than at least the cycle of the first signal after said second driving unit asserted the second data signal line, the inversion of the logical value by said second switching unit by cancelling the assertion of the second data signal line while deciding that said master apparatus is in a communicable state.