System and method for controlling at least two power semiconductors connected in parallel

摘要

A system includes at least two power semiconductor chips being connected in parallel and including each a gate terminal for switching the power semiconductor chip in a blocking-state by a first gate voltage and for switching the power semiconductor chip in a conducting-state by a second gate voltage. The system includes further a control device adapted for applying the first or the second gate voltage to the gate terminals of the at least two power semiconductor chips. The control device is adapted for applying a third gate voltage to the gate terminal of the at least one remaining power semiconductor chip when a power semiconductor chip fails, and that the third gate voltage is higher than the second gate voltage.

主权项

1. A system comprising:
at least two power semiconductor chips being connected in parallel and comprising each a gate terminal for switching the power semiconductor chip in a blocking-state by a first gate voltage and for switching the power semiconductor chip in a conducting-state by a second gate voltage; and a control device adapted to apply the first or the second gate voltage to the gate terminals of the at least two power semiconductor chips and adapted to detect a failure of one of the at least two power semiconductor chips, wherein the control device is adapted to apply, when a power semiconductor chip of the at least two power semiconductor chips fails and enters a short circuit failure mode, SCFM, a third gate voltage to the gate terminal of the at least one remaining power semiconductor chip, and in that the third gate voltage is higher than the second gate voltage, and the third gate voltage is applied permanently to the gate terminal of the at least one remaining power semiconductor chip when a power semiconductor chip fails.