Methods for Double-Patterning-Compliant Standard Cell Design

摘要

A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

主权项

1. A method comprising:
determining candidate cells of a half-pitch technology in an integrated circuit cell library, each of the candidate cells having one or more features; determining a first design rule selected from the group consisting of an odd-number-only rule and an even-number-only rule; selecting a first group of cells from the candidate cells, with the first group of cells being compliant with the first design rule; and placing the first group of cells into a first row of an integrated circuit such that cells of the first group of cells are immediately adjacent to neighboring cells and, with the first row having neighboring cells compliant with the first design rule; wherein G0 paths in the first group of cells represent first distances between adjacent pairs of features that are less than a minimum spacing allowed by the half-pitch technology; wherein double-patterning full traces in the first group of cells represent G0 paths contiguously traversing from a VDD line to a VSS line; wherein the odd-number-only rule requires that each double-patterning full trace traversing cells in the first group of cells have only an odd number of G0 paths; and wherein the even-number-only rule requires that each double-patterning full trace traversing cells in the first group of cells have only an even number of G0 paths.