发明名称 DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT
摘要 A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved.
申请公布号 US2015095741(A1) 申请公布日期 2015.04.02
申请号 US201314109959 申请日期 2013.12.18
申请人 PHISON ELECTRONICS CORP. 发明人 Lin Wei;Yen Shao-Wei;Lin Yu-Hsiang;Lai Kuo-Hsin;Cheng Kuo-Yi
分类号 G06F11/10 主分类号 G06F11/10
代理机构 代理人
主权项 1. A decoding method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, the decoding method comprising: reading a plurality of first memory cells of the memory cells according to at least one first reading voltage to obtain at least one first verifying bit of each of the first memory cells; executing a first decoding procedure comprising a probability decoding algorithm according to the at least one first verifying bits of the first memory cells to obtain a plurality of first decoded bits, and determining whether a decoding is successful by using the first decoded bits; and if the decoding is failed, reading the first memory cells according to at least one second reading voltage to obtain at least one second verifying bit of each of the first memory cells, and executing the first decoding procedure according to the at least one second verifying bits of the first memory cells to obtain a plurality of second decoded bits, wherein the at least one second reading voltage is different from the at least one first reading voltage, and the number of the at least one second reading voltage is equal to the number of the at least one first reading voltage.
地址 Miaoli TW
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