发明名称 METHOD FOR THE FORMATION OF CMOS TRANSISTORS
摘要 An SOI substrate includes first and second active regions separated by STI structures and including gate stacks. A spacer layer conformally deposited over the first and second regions including the gate stacks is directionally etched to define sidewall spacers along the sides of the gate stacks. An oxide layer and nitride layer are then deposited. Using a mask, the nitride layer over the first active region is removed, and the mask and oxide layer are removed to expose the SOI substrate in the first active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the first active region and a protective nitride layer is deposited. The masking, nitride layer removal, and oxide layer removal steps are then repeated to expose the SOI in the second active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the second active region.
申请公布号 US2015093861(A1) 申请公布日期 2015.04.02
申请号 US201314042884 申请日期 2013.10.01
申请人 STMicroelectronics, Inc. 发明人 Loubet Nicolas;Liu Qing;Khare Prasanna
分类号 H01L21/84 主分类号 H01L21/84
代理机构 代理人
主权项 1. A method, comprising: forming shallow trench isolation structures on a silicon on insulator (SOI) substrate to define for a wafer a first active region for first conductivity type transistor fabrication separated from a second active region for second conductivity type transistor fabrication; forming a first gate stack over a top semiconductor layer of the SOI substrate in the first active region and a second gate stack over the top semiconductor layer of the SOI substrate in the second active region; conformally depositing a spacer layer on the wafer over the first and second active region; anisotropically etching the wafer to remove the spacer layer except from sidewalls of the first and second gate stacks so as to define sidewall spacers on said first and second gate stacks; forming an oxide layer on the wafer to cover the SOI substrate, shallow trench isolation structures, sidewall spacers and gate stacks; and forming a nitride layer on the wafer over the oxide layer.
地址 Coppell TX US