SYSTEM ON CHIP INCLUDING CONFIGURABLE IMAGE PROCESSING PIPELINE AND SYSTEM INCLUDING THE SAME

摘要

A system on chip (SoC) including a configurable image processing pipeline is provided. The SoC includes a bus; a first image processing module configured to be connected to the bus and to process image data; a first image processing stage configured to transmit either first image data or second image data received from the bus to at least one of the bus and the first image processing module through a first bypass path in response to first control signals; and a second image processing stage configured to transmit either third image data received from the first image processing module or fourth image data received from the bus to the bus through one of a second bypass path and a second scaler path in response to second control signals.

主权项

1. A system on chip (SoC) comprising:
a bus; a first image processing module having a second input, for receiving image data, switchably connected to the bus, and configured to process the received image data into third image data; a first image processing stage configured to transmit either
first image data orsecond image data received from the bus as the received image data to at least one of
the bus andthe first image processing module in response to first control signals; and a second image processing stage configured to transmit either
the third image data received from the first image processing module orfourth image data received from the bus to the bus through one of
a second bypass path anda second scaler path including a second scaler in response to second control signals.