| 摘要 |
A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit stream, done tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit as part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that once data has arrived at its destination it is properly locked, not to be unintentionally overwritten. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration. |
| 主权项 |
1. A flexible logic unit comprising:
a first clock and a second clock, the first clock and the second clock being non-recovering clocks; a matrix having a plurality of tiles arranged in columns and rows, each tile having at least one latch bank therein, each latch bank within any one column having an identical number of one or more latches therein, each tile having configurable logic configurable responsive to configuration data stored in the respective latch bank, the latches in each latch bank being clocked in unison for that latch bank, each of the latch banks being arranged to accept configuration data from an immediately previous latch bank in that column, such that one latch bank is clocked by the first clock if an immediately previous latch bank in the same column is clocked by the second clock or by the second clock if an immediately previous latch bank in the same column is clocked by the first clock, each column of the matrix being configured to accept configuration data in a first configuration data flow direction within the column; a plurality of lock flip-flops arranged in columns, each lock flip-flop corresponding to a respective latch bank of a respective column of the matrix, the plurality of lock flip-flops configured to accept a lock bit in a lock bit flow direction that is opposite to the configuration data flow direction, one lock flip-flop being clocked by the first clock if an immediately previous lock flip-flop in the same column is clocked by the second clock or by the second clock if an immediately previous lock flip-flop in the same column is clocked by the first clock; a control interface to accept at least a configuration word for each latch bank and associated lock flip-flop, the interface configured to separate, for each column, configuration data and lock bits data from the configuration words; a plurality of data busses, one for each column of the matrix configured to receive data from each of the one or more latches in each of the latch banks of each column; a cyclic redundancy check control circuit providing a plurality of row select signals and a plurality of word select signals for selection of a particular latch bank in a particular row and enable the loading of configuration data stored therein onto a corresponding data bus of the plurality of data busses, the cyclic redundancy check control circuit configured to begin operating when the flexible logic unit completes data configuration; and a plurality of cyclic redundancy check circuits, each corresponding to one of the plurality of data busses, each cyclic redundancy check circuit configured to process cyclic redundancy check data to generate an error state on at least an error signal of at least one of the plurality of the cyclic redundancy check circuits, upon the plurality of cyclic redundancy check circuits receiving configuration data from all of the one or more latches in the one or more latch banks of a corresponding column and determination that an error has been found respective thereof. |
