| 发明名称 |
METHOD FOR MAKING AN INTEGRATED CIRCUIT |
| 摘要 |
A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity. |
| 申请公布号 |
US2015091106(A1) |
申请公布日期 |
2015.04.02 |
| 申请号 |
US201414498091 |
申请日期 |
2014.09.26 |
| 申请人 |
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ;STMICROELECTRONICS SA ;STMICROELECTRONICS (Crolles 2) SAS |
发明人 |
BARNOLA SÉBASTIEN;MORAND YVES;NIEBOJEWSKI HEIMANU |
| 分类号 |
H01L21/28;H01L29/49;H01L29/423;H01L29/78;H01L21/283;H01L29/66 |
主分类号 |
H01L21/28 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for making an integrated circuit on a substrate, comprising:
making a gate stack on a surface of an active zone, the making comprising: depositing a first layer of dielectric which extends over the active zone; depositing a gate conductive layer which extends over the layer of first dielectric; depositing a layer of a first metal which extends over the gate conductive layer; depositing a layer of a second metal which extends over the layer of the first metal; depositing a layer of a second dielectric which extends over the layer of the second metal;partially etching the gate stack for the formation of a gate zone on the active zone;making insulating spacers on either side of the gate zone on the active zone;making source and drain zones;making silicidation zones on a surface of the source and drain zones;etching, in the gate zone on the active zone, the second dielectric layer and the layer of second metal with stopping on the layer of the first metal, so as to form a cavity between the insulating spacers; andmaking a protective plug at a surface of the layer of first metal of the gate zone on the active zone, wherein the protective plug fills the cavity. |
| 地址 |
Paris FR |
