REDUCING A SETTLING TIME AFTER A SLEW CONDITION IN AN AMPLIFIER

摘要

In an amplifier, a first stage receives a differential input voltage, which is formed by first and second input voltages, and outputs a first differential current in response thereto on first and second lines having respective first and second line voltages. A second stage receives the first and second line voltages and outputs a second differential current in response thereto on third and fourth lines having respective third and fourth line voltages. A third stage receives the third and fourth line voltages and outputs an output voltage in response thereto. A slew boost circuit detects a slew condition, in which a threshold difference arises between the first and second input voltages, and outputs a slew current in response thereto for maintaining a slew rate of the output voltage during the slew condition. The first stage includes circuits for reducing a variable difference between the first and second line voltages.

主权项

1. An amplifier, comprising:
a first stage for receiving a differential input voltage, which is formed by first and second input voltages, and outputting a first differential current in response thereto on first and second lines having respective first and second line voltages; a second stage coupled to the first stage for receiving the first and second line voltages and outputting a second differential current in response thereto on third and fourth lines having respective third and fourth line voltages; a third stage coupled to the second stage for receiving the third and fourth line voltages and outputting an output voltage in response thereto; and a slew boost circuit coupled to the third stage for detecting a slew condition, in which a threshold difference arises between the first and second input voltages, and outputting a slew current in response thereto for maintaining a slew rate of the output voltage during the slew condition, and wherein the slew current causes a variable difference to increase between the first and second line voltages; wherein the first stage includes: a first circuit for reducing the variable difference in response to the first line voltage exceeding the second line voltage; and a second circuit for reducing the variable difference in response to the second line voltage exceeding the first line voltage; wherein the first circuit includes a first transistor whose gate is coupled to the first line, a second transistor whose gate is coupled to the second line, and a third transistor whose gate is coupled to a source/drain of the second transistor, and wherein the second line is coupled to a source/drain of the third transistor; and wherein the second circuit includes a fourth transistor whose gate is coupled to the first line, a fifth transistor whose gate is coupled to the second line, and a sixth transistor whose gate is coupled to a source/drain of the fifth transistor, and wherein the second line is coupled to a source/drain of the sixth transistor.