Circuit And Method For Monolithic Stacked Integrated Circuit Testing

摘要

A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of its upper layers. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the stacked IC may be conducted on a layer-by-layer basis.

主权项

1. A monolithic stacked integrated circuit (IC) comprising a known-good-layer (KGL) test circuit and a scan segment in a first layer of the IC, wherein the first layer is an upper layer of the IC, the KGL test circuit comprising:
a first test input, coupled to an input of the scan segment, to receive a first scan shift data; a first multiplexer, the first multiplexer having a first data input, a second data input, a first selection input, and a first data output wherein the first data input is coupled to the first test input and the second data input is coupled to an output of the scan segment; a first test output, coupled to the first data output, to send a second scan shift data to a second layer; a second test input, to receive a third scan shift data from the second layer; a second multiplexer, the second multiplexer having a third data input, a fourth data input, a second selection input, and a second data output wherein the third data input is coupled to the second test input and the fourth data input is coupled to the first data output; a second test output, coupled to the second data output, to send a fourth scan shift data; a first control element, coupled to the first selection input; and a second control element, coupled to the second selection input.