VECTOR INDEXED MEMORY ACCESS PLUS ARITHMETIC AND/OR LOGICAL OPERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

摘要

A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is to indicate a source packed memory indices operand that is to have a plurality of packed memory indices. The instruction is also to indicate a source packed data operand that is to have a plurality of packed data elements. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.

主权项

1. A processor comprising:
a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction, the vector indexed load plus A/L operation plus store instruction to indicate a source packed memory indices operand that is to have a plurality of packed memory indices, and to indicate a source packed data operand that is to have a plurality of packed data elements; and an execution unit coupled with the decode unit, the execution unit, in response to the vector indexed load plus A/L operation plus store instruction, to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, to perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and to store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.