PARALLEL HARDWARE AND SOFTWARE BLOCK PROCESSING PIPELINES

摘要

A block processing pipeline that includes a software pipeline and a hardware pipeline that run in parallel. The software pipeline runs at least one block ahead of the hardware pipeline. The stages of the pipeline may each include a hardware pipeline component that performs one or more operations on a current block at the stage. At least one stage of the pipeline may also include a software pipeline component that determines a configuration for the hardware component at the stage of the pipeline for processing a next block while the hardware component is processing the current block. The software pipeline component may determine the configuration according to information related to the next block obtained from an upstream stage of the pipeline. The software pipeline component may also obtain and use information related to a block that was previously processed at the stage.

主权项

1. An apparatus, comprising:
a block processing pipeline comprising a plurality of stages, wherein one or more of the plurality of stages of the block processing pipeline each comprises a component of a software pipeline and a component of a hardware pipeline, wherein the software and hardware pipelines are configured to process blocks of pixels from a frame in parallel; wherein the software pipeline component at each of the one or more stages is configured to iteratively determine configurations for processing the blocks at the hardware pipeline component of the stage according to obtained information for the blocks; wherein the hardware pipeline component at each of the one or more stages is configured to iteratively process the blocks according to the configurations for processing the blocks that are determined by the software pipeline component at the stage; and wherein the hardware pipeline component at each of the one or more stages processes a current block at the stage while the software pipeline component at the stage is determining a configuration for an upcoming block to be processed by the hardware pipeline component at the stage.