METHOD AND DEVICES FOR TIME AND FREQUENCY SYNCHRONIZATION USING A PHASE LOCKED LOOP

摘要

This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.

主权项

1. A slave device connected to a master device having a master clock over a network, wherein the slave device includes:
a slave clock; and a digital phase locked loop including a phase detector, a loop filter, a phase accumulator and a counter, wherein: the slave device is arranged to:
exchange with the master device, timing messages and to record timestamps which are: the time of sending of said timing messages from the master device according to the master clock; the time of receipt of said timing messages according to the slave clock; the time of sending of said timing messages according to the slave clock; and the time of receipt of said timing messages according to the master clock,estimate the skew and offset of the slave clock relative to the master clock from said timestamps; andsynchronize said slave clock to the master clock based on the estimated skew and offset to produce a master time estimate; the digital phase locked loop processes the master time estimate as follows:
on receipt of a first estimate of the master time, the counter is initialised;on receipt of subsequent estimates of the master time, the phase detector is arranged to detect a phase difference between the output of the counter and the received estimate and produce an error signal representing that difference;the error signal is filtered by the loop filter to produce a filtered error signal;the filtered error signal is used to control the frequency of the phase accumulator; andthe output of the phase accumulator increments the counter and also provides a clock frequency of the slave clock which is synchronized to the frequency of the master clock.