| 发明名称 |
POWER DISTRIBUTION FOR 3D SEMICONDUCTOR PACKAGE |
| 摘要 |
A method including a printed circuit board electrically coupled to a bottom of a laminate substrate, the laminate substrate having an opening extending through the entire thickness of the laminate substrate, a main die electrically coupled to a top of the laminate substrate, a die stack electrically coupled to a bottom of the main die, the die stack including one or more chips stacked vertically and electrically coupled to one another, the die stack extending into the opening of the laminate substrate, and an interposer positioned between and electrically coupled to a topmost chip and the printed circuit board, the interposer providing an electrical path from the printed circuit board to the topmost chip of the die stack. |
| 申请公布号 |
US2015091131(A1) |
申请公布日期 |
2015.04.02 |
| 申请号 |
US201314041277 |
申请日期 |
2013.09.30 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Lamorey Mark C.;Patel Janak G.;Slota, JR. Peter;Stone David B. |
| 分类号 |
H01L25/00;H01L23/00;H01L25/18 |
主分类号 |
H01L25/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A structure comprising:
a printed circuit board electrically coupled to a bottom of a laminate substrate, the laminate substrate having an opening extending through an entire thickness of the laminate substrate; a main die electrically coupled to a top of the laminate substrate; a die stack electrically coupled to a bottom of the main die, the die stack comprising one or more chips stacked vertically and electrically coupled to one another, the die stack extending into the opening of the laminate substrate; and an interposer positioned between and electrically coupled to a topmost chip of the die stack and the printed circuit board, the interposer providing an electrical path from the printed circuit board to the topmost chip of the die stack. |
| 地址 |
Armonk NY US |
