发明名称 |
HIGH CAPACITY MEMORY SYSTEM |
摘要 |
The embodiments described herein describe technologies for memory systems. One implementation of a memory module includes multiple device sites coupled to the a data query (DQ) buffer component via data lines and coupled to a command and address (CA) buffer component via chip select (CS) lines. A first number of the CS lines between the CA buffer component and any combination of two or more of the multiple device sites is greater than a second number of the CS lines between the CA buffer component and a single one of the multiple device sites. |
申请公布号 |
WO2015048199(A1) |
申请公布日期 |
2015.04.02 |
申请号 |
WO2014US57314 |
申请日期 |
2014.09.24 |
申请人 |
RAMBUS INC. |
发明人 |
WARE, FREDERICK A.;RAJAN, SURESH |
分类号 |
G11C7/10 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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