DUAL PORT SRAM WITH DUMMY READ RECOVERY

摘要

An integrated includes a dual port memory cell such as a SRAM cell. A first port dummy read recovery block couples the first port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the second port bit line, and couples the first port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the second port complementary bit line. A second port dummy read recovery block couples the second port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the first port bit line, and couples the second port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the first port complementary bit line.

主权项

1. An integrated circuit, comprising:
a first port word line; a second port word line; a first port bit line and a first port complementary bit line; a second port bit line and a second port complementary bit line; a dual port memory cell having a data node coupled to the first and second port bit lines under control of the first and second port word lines and a complementary data node coupled to the first and second port complementary bit lines under control of the first and second port word lines; a first port dummy read recovery block configured to couple the first port complementary bit line to a high voltage supply node during a write logic low operation to the data node of the memory cell through the second port bit line, and to couple the first port bit line to a high voltage supply node during a write logic low operation to the complementary data node of the memory cell through the second port complementary bit line; and a second port dummy read recovery block configured to couple the second port complementary bit line to a high voltage supply node during a write logic low operation to the data node of the memory cell through the first port bit line, and to couple the second port bit line to a high voltage supply node during a write logic low operation to the complementary data node of the memory cell through the first port complementary bit line.