SINGLE EVENT TRANSIENT-RESISTANT CMOS CIRCUIT

摘要

An single event transient (SET)-resistant CMOS circuit. The circuit consists of a first buffer (101), a second buffer (102), a gating PMOS transistor (103), a gating NMOS transistor (104) and a phase inverter (105); the first buffer is used for eliminating 'high-low-high' pulse, the input end of the first buffer is connected with the input end of an SET-resistant circuit, and the output end of the first buffer is connected with a grid of the gating PMOS transistor (103); the second buffer is used for eliminating 'low-high-low' pulse, the input end of the second buffer is connected with the input end of the SET-resistant circuit, and the output end of the second buffer is connected with a grid of the gating NMOS transistor (104). A drain of the gating PMOS transistor (103) is connected with a drain of the gating NMOS transistor (104) and serves as the input end of the phase inverter (105); and the output end of the phase inverter serves as the output end of the SET-resistant circuit.