发明名称 |
SYSTEM AND METHOD FOR THREAD SCHEDULING ON RECONFIGURABLE PROCESSOR CORES |
摘要 |
Systems and methods for efficiently utilizing reconfigurable processor cores. An example processing system includes, for example, a control register comprising a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and dynamic core reallocation logic to temporarily merge a first processor core and a second processor core to speed execution of a first thread executed on the first processor core responsive to determining that a second thread executed on the second processor core has completed execution prior to a quantum associated with the second thread being reached and to determining that the inhibit bits indicate that the first and second cores may be merged. |
申请公布号 |
US2015095918(A1) |
申请公布日期 |
2015.04.02 |
申请号 |
US201314040142 |
申请日期 |
2013.09.27 |
申请人 |
Alameldeen Alaa R.;Wilkerson Christopher B.;Gorbatov Eugene;Chishti Zeshan A. |
发明人 |
Alameldeen Alaa R.;Wilkerson Christopher B.;Gorbatov Eugene;Chishti Zeshan A. |
分类号 |
G06F9/50;G06F12/08 |
主分类号 |
G06F9/50 |
代理机构 |
|
代理人 |
|
主权项 |
1. A processing system, comprising:
a plurality of processor cores; a control register comprising a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and dynamic core reallocation logic to temporarily merge a first processor core and a second processor core to speed execution of a first thread executed on the first processor core responsive to determining that a second thread executed on the second processor core has completed execution prior to a quantum associated with the second thread being reached and to determining that the inhibit bits indicate that the first and second cores may be merged. |
地址 |
Hillsboro OR US |