发明名称 INTEGRATED CIRCUIT AND CODE GENERATING METHOD
摘要 An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.
申请公布号 US2015091747(A1) 申请公布日期 2015.04.02
申请号 US201314038772 申请日期 2013.09.27
申请人 PHISON ELECTRONICS CORP. 发明人 Watanabe Hiroshi
分类号 G08C19/28;H01L29/78;H01L27/105 主分类号 G08C19/28
代理机构 代理人
主权项 1. An integrated circuit, comprising: at least one first input/output end; at least one current path, connected with the first input/output end; at least one control end, disposed above the at least one current path, configured to apply a plurality of control end voltages on the at least one current path; and at least one second input/output end, connected with the current path; wherein, the width and the thickness of the current path are defined according to the de Broglie length (DBL), and the length of the current path is longer than the width and the thickness of the current path.
地址 Miaoli TW