| 发明名称 |
REDUCING CURRENT VARIATION WHEN SWITCHING CLOCKS |
| 摘要 |
An apparatus includes a glitchless divider and a glitchless multiplexer. The glitchless divider may be configured to generate a first system clock in response to a divider value and a clock signal received from a first source. The divider value changes from a first value to a second value in a predetermined number of steps. The glitchless multiplexer may be configured to select between said first system clock and a second system clock in response to a control signal. |
| 申请公布号 |
US2015091620(A1) |
申请公布日期 |
2015.04.02 |
| 申请号 |
US201314045295 |
申请日期 |
2013.10.03 |
| 申请人 |
LSI Corporation |
发明人 |
Pollock Steven J. |
| 分类号 |
H03K17/16 |
主分类号 |
H03K17/16 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a glitchless divider configured to generate a first system clock in response to a divider value and a clock signal received from a first source, wherein said divider value changes from a first value to a second value in a predetermined number of steps; and a glitchless multiplexer configured to select between said first system clock and a second system clock in response to a control signal. |
| 地址 |
San Jose CA US |
