| 发明名称 |
ARITHMETIC PROCESSING UNIT, AND METHOD OF CONTROLLING ARITHMETIC PROCESSING UNIT |
| 摘要 |
An arithmetic processing unit including a memory controller configured to make variable-length access requests allowing a plurality of lengths to a memory, the memory controller comprising: a plurality of buffers configured to hold the access requests for each of the lengths of the access requests; and an arbitrator configured to select one of access requests stored in the plurality of buffers in accordance with a number of remaining resources of the memory. |
| 申请公布号 |
US2015095621(A1) |
申请公布日期 |
2015.04.02 |
| 申请号 |
US201414457461 |
申请日期 |
2014.08.12 |
| 申请人 |
FUJITSU LIMITED |
发明人 |
Toyoda Yuta;Hosoe Koji;Tokoyoda Akio;Aihara Masatoshi;Suga Makoto |
| 分类号 |
G06F9/30;G06F13/366 |
主分类号 |
G06F9/30 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An arithmetic processing unit including a memory controller configured to make variable-length access requests allowing a plurality of lengths to a memory, the memory controller comprising:
a plurality of buffers configured to hold the access requests for each of the lengths of the access requests; and an arbitrator configured to select one of access requests stored in the plurality of buffers in accordance with a number of remaining resources of the memory. |
| 地址 |
Kawasaki-shi JP |
