发明名称 |
CIRCUIT DESIGN SUPPORT METHOD, COMPUTER PRODUCT, CIRCUIT DESIGN SUPPORT APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
A circuit design support method includes obtaining layout data that indicates positions of a plurality of clock receivers disposed in a circuit and positions of first clock wires disposed in the circuit; and calculating, by a computer, a value corresponding to lengths of wires respectively connecting the clock receivers to second clock wires on the basis of the obtained layout data, the value being calculated for each of a plurality of combinations of a count of the second clock wires and positions of the second clock wires, the second clock wires being disposed in a wiring layer of the circuit and being perpendicular to the first clock wires. |
申请公布号 |
US2015095871(A1) |
申请公布日期 |
2015.04.02 |
申请号 |
US201414497876 |
申请日期 |
2014.09.26 |
申请人 |
FUJITSU SEMICONDUCTOR LIMITED |
发明人 |
Kitaura Tomoyasu |
分类号 |
G06F17/50;H01L27/02 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A circuit design support method comprising:
obtaining layout data that indicates positions of a plurality of clock receivers disposed in a circuit and positions of first clock wires disposed in the circuit; and calculating, by a computer, a value corresponding to lengths of wires respectively connecting the clock receivers to second clock wires on the basis of the obtained layout data, the value being calculated for each of a plurality of combinations of a count of the second clock wires and positions of the second clock wires, the second clock wires being disposed in a wiring layer of the circuit and being perpendicular to the first clock wires. |
地址 |
Yokohama-shi JP |