VLSI CIRCUIT SIGNAL COMPRESSION

摘要

An embedded agent (104) of an integrated circuit (102) includes a collector (220) configured to receive from a tested target circuit a plurality of single bit lines of signals and a signal canceller (322) configured to receive an indication of lines that are not to be exported, for a given time period, and to set the indicated lines to a constant value. A linear combination calculation circuit (402) configured to generate a plurality of different linear combinations of the values of the single bit lines, for the clock cycles of the given time period, is also included in the embedded agent. A transmitter (216) exports from the chip a sub-group of the linear combinations calculated by the linear combination calculation circuit for the clock cycles of the given time period, the sub-group including a number of linear combinations selected responsively to the number of lines set to a constant value.

主权项

1. An integrated circuit, comprising:
a target circuit on a chip; and an embedded agent on the chip, including:
a signal collector configured to collect from the target circuit signals of a plurality of single bit lines;a signal canceller configured to receive an indication of lines that are not to be exported, for a given time period, and to set the indicated lines to a constant value, for the given time period;a linear combination calculation circuit configured to generate a plurality of different linear combinations of the values of the single bit lines, for the clock cycles of the given time period; anda transmitter configured to export from the chip a sub-group of the linear combinations calculated by the linear combination calculation circuit for the clock cycles of the given time period, the sub-group including a number of linear combinations selected responsively to the number of lines set to a constant value.