METHOD AND PROCESSOR FOR REDUCING CODE AND LATENCY OF TLB MAINTENANCE OPERATIONS IN A CONFIGURABLE PROCESSOR

摘要

A memory management unit (MMU) is disclosed for storing mappings between virtual addresses and physical addresses. The MMU includes a translation look-aside buffer (TLB) and a memory management unit controller. The TLB stores mappings between a virtual address and a physical address. The MMU controller receives a request to insert an entry into the TLB and performs a set of operations based on the received request. The MMU controller determines whether an entry stored in the TLB is associated with the virtual address of the request, removes the entry stored in the TLB that is associated with the virtual address and inserts the requested entry into the TLB.

主权项

1. A memory management unit (MMU) for storing mappings between virtual addresses and physical addresses, the MMU comprising:
a translation look-aside buffer (TLB) configured to store mappings between virtual address and physical address; and a memory management unit (MMU) controller configured to:
receive a request to insert a an entry into the TLB, the request comprising a virtual address and a physical address, andresponsive to receiving the request to insert the entry:
determining whether a stored entry in the TLB is associated with the virtual address of the requested entry by comparing the virtual address of the requested entry to a virtual address associated with each stored entry in the TLB;responsive to determining that the stored entry is associated with the virtual address, removing the stored entry; andinserting the requested entry into the TLB.