Latency-Aware Memory Control

摘要

A system, method and computer-readable storage device for accessing heterogeneous memory system, are provided. A memory controller schedules access of a command to a memory region in a set of memory regions based on an access priority associated with the command and where the set of memory regions have corresponding access latencies. The memory controller also defers access of the command to the set of memory regions using at least two queues and the access priority.

主权项

1. A system comprising:
a memory controller configured to:
schedule access by a command to a memory region from a set of memory regions based on an access priority associated with the command, wherein the set of memory regions have corresponding access latencies; anddefer access by the command to the memory region using at least two queues and the access priority.