发明名称 MULTIPLE SILICON TRENCHES FORMING METHOD FOR MEMS SEALING CAP WAFER AND ETCHING MASK STRUCTURE THEREOF
摘要 A multiple silicon trenches forming method and an etching mask structure, the method comprises: step S11, providing a MEMS sealing cap silicon substrate (100); step S12, forming n stacked mask layers (101, 102, 103) on the MEMS sealing cap silicon substrate (100), after forming each mask layer, photolithographing and etching the mask layer and all other mask layers beneath the same to form a plurality of etching windows (D1, D2, D3); step S13, etching the MEMS sealing cap silicon substrate by using the current uppermost mask layer and a layer of mask material beneath the same as a mask; step S14, removing the current uppermost mask layer; step S15, repeating the step S13 and the step S14 until all the n mask layers are removed. The present invention can form a plurality of deep trenches with high aspect ratio on the MEMS sealing cap silicon substrate using conventional semiconductor processes, avoiding the problem that the conventional spin coating cannot be conducted on a sealing cap wafer with deep trenches using photoresist.
申请公布号 US2015091140(A1) 申请公布日期 2015.04.02
申请号 US201314389565 申请日期 2013.03.18
申请人 HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD 发明人 Wen Yongxiang;Liu Chen;Ji Feng;Li Liwen
分类号 B81C1/00;B81B7/00 主分类号 B81C1/00
代理机构 代理人
主权项 1. A multiple silicon trenches forming method for MEMS sealing cap wafer, characterized in comprising: step S11, providing a MEMS sealing cap silicon substrate; step S12, forming n stacked mask layers on the MEMS sealing cap silicon substrate, after forming each mask layer, photolithographing and etching the mask layer and all other mask layers beneath the same to form multiple etching windows, wherein n is a positive integer greater than or equal to 2, and any two adjacent mask layers are made of different materials; step S13, etching the MEMS sealing cap silicon substrate by using a current uppermost mask layer in the n mask layers as a mask, with an etching selectivity ratio of the MEMS sealing cap silicon substrate to the current uppermost mask layer greater than or equal to 10:1; step S14, removing the current uppermost mask layer; step S15, repeating the step S13 and the step S14 until all the n mask layers are removed.
地址 Hangzhou (Xiasha) CN