| 摘要 |
In order to develop a circuit arrangement (100) and also a method for calibrating at least one activation signal (Vbb) provided for a voltage-controlled oscillator (10) such that the expenditure of energy is as low as possible and the output frequency is as high as possible, it is proposed—that the respective number of clock cycles (N) for at least one calibration oscillator (50) and at least one reference oscillator (30) associated with the calibration oscillator (50) is counted by means of at least one clock cycle counter (70) connected downstream of the calibration oscillator (50) and the reference oscillator (30) and a clock error (DE) resulting from the difference between these two numbers of clock cycles (N) is integrated and—that the clock error (DE) is converted by means of at least one digital-to-analogue converter (90) connected downstream of the clock counter (70) into analogue tuning signals (Vcm, Vcm−, Vcm+) from which the calibrated activation signal (Vbb) is derived. |
