Multiple core processing with high throughput atomic memory operations

摘要

A processor 100 comprises multiple processor cores 102, 102', 102" and a bus 116 for exchanging data between the cores. Each of the cores comprises: at least one processor register; a cache 108 for storing at least one cache line of memory; a load store unit 104 for executing a memory command to exchange data between the cache and the processor register; an atomic memory operation unit 110 for executing an atomic memory operation on the at least one cache line of memory; and a high throughput register 112 for storing a status indicating either a high throughput or a normal status. The load store unit is operable to transfer (114) the atomic memory operation to the atomic memory operation unit of a designated processor core (102") via the bus, if the high throughput register indicates the high throughput status. This allows faster processing of atomic operations without needing to transfer the cache line between cores.