发明名称 配线基板及其制造方法;WIRING SUBSTRATE AND MANUFACTURING METHOD THEREOF
摘要 本发明之配线基板10系具备:下层之配线导体1;上层之绝缘层2,积层在下层之配线导体1上,且具有以下层之配线导体1为底面之介层孔5;及介层导体3,连接在下层之配线导体1且填充于介层孔5内;其中,上层之绝缘层2系具有依序积层在下层之配线导体1上的第1树脂层2a、及第2树脂层2b,介层孔5系在第1树脂层2a与第2树脂层2b之交界,具有介层孔5之内壁遍及全周地凹入之环状之沟槽部5a,且介层导体3系以咬入沟槽部5a内之方式被填充。; an upper layer insulating layer 2 laminated on the lower layer wiring conductor 1 and having a via hole 5 having a bottom surface on the lower layer wiring conductor 1; and a via conductor 3 connected to the lower layer wiring conductor 1 and filled into the via hole 5; wherein the lower layer insulating layer 2 has a first resin layer 2a and a second resin layer 2b sequentially laminated on the lower layer wiring conductor 1, the via hole 5 has an annular trench portion 5a concaving in an inner periphery of an interior wall of the via hole 5 at the boundary between the first resin layer 2a and the second resin layer 2b, and the via conductor 3 is filled to bite into the trench portion 5a.
申请公布号 TW201513749 申请公布日期 2015.04.01
申请号 TW103117879 申请日期 2014.05.22
申请人 京瓷SLC技术股份有限公司 KYOCERA SLC TECHNOLOGIES CORPORATION 发明人 汤川英敏 YUGAWA, HIDETOSHI
分类号 H05K1/11(2006.01);H05K3/40(2006.01) 主分类号 H05K1/11(2006.01)
代理机构 代理人 洪武雄陈昭诚
主权项
地址 日本 JP